Electronic Design

Combining Logic BIST and Scan Test Compression

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...
Design-Reuse

LogicVision Announces Production Release of Memory Built-In Self-Repair and ScanBurst At-Speed Scan Solution Integrated With Mentor Graphic's FastScan and TestKompress

New Release Provides Support for Verilog2001 and a Wide Range of Usability Improvements across the Built-In Self-Test Product Line SAN JOSE, Calif. -- Aug. 21, 2007 -- LogicVision, Inc., a leading ...
Design-Reuse

DFT for SoC : The Economic Myths

It is often said that the emergence of the System-on-Chip will require fundamental changes in the approaches to design for testability (DFT.) These changes, it has been suggested, will take the form ...
Electronic Design

DFT Strategies for SOC Designs

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...