EDN

Synthesis tool links MATLAB with ASIC, FPGA designs

MILPITAS, Calif. — AccelChip has crafted a DSP synthesis tool that converts algorithms developed in MATLAB into synthesizable RTL that can be used during the design of FPGAs, ASICs and structured ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
EDN

The “Missing Link” of SoC Design—Platform and Structured ASICs

Are ASIC designs too expensive? Does FPGA performance fall short of specifications? Consider a structured or platform ASIC implementation for your next mid-performance, mid-volume chip. Over the past ...
Design-Reuse

Structured ASIC Based SoC Design

Complex System-on-Chip (SoC) designs are fast becoming commonplace in today’s applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market (TTM), ...
Ars Technica

Breaking into ASIC Design/Verification

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...
Design-Reuse

FPGA to ASIC Strategy for Communication SoC Designs

Current communication systems utilize highly complex SoC designs for numerous applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market, ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Electronics Weekly

Taking the road from ASIC to FPGA

Guest columnist Tom Feist, director of tools marketing at Xilinx restates the arguments for considering FPGAs – no DFM, no mask prep, no DRC/LVS If you’ve been in the electronics industry even just a ...
Electronic Design

Understanding FPGA Processor Interconnects

This file type includes high resolution graphics and schematics when applicable. FPGAs are wonderful tools. They consist of a collection of logic cells called lookup tables (LUTs) surrounded by an ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...