Business Wire

MathWorks Speeds Up FPGA-in-the-Loop Verification

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with ...
Hackaday

MATLAB And Simulink For Zynq

Although we see a lot of MATLAB use in industry and in academia, it isn’t as popular in the hacker community. That’s probably due to the cost. If you’ve ever wondered why companies will pay over $2000 ...
EDN

FPGA video programming with Agility’s graphical environment

To make FPGAs accessible to DSP engineers without hardware design expertise, FPGA and tool vendors have developed tools that allow FPGAs to be programmed in high-level behavioral languages such as ...
Electronics Weekly

Microsemi and MathWorks support FPGA-in-the-loop verification

Microsemi and MathWorks launched hardware support for FPGA-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The integrated FIL workflow with HDL Coder and HDL Verifier ...
Electronic Design

Mentor Graphics, Mathworks Optimize FPGA Design Flow

Mentor Graphics has upgraded its Precision Synthesis tool to include hardware description language (HDL) generated by MathWorks Simulink HDL Coder. Customers will be able to transfer VHDL and Verilog ...